1. Field of the Invention
The present invention relates to a flash cell structure and a method of fabricating the same, and more particularly to a flash cell structure having a thickness of a dielectric layer between an erase gate and a floating gate less than a thickness of the dielectric layer between the erase gate and a source and a method of fabricating the same.
2. Description of the Prior Art
Communication of mass information is a feature of modern life. Memory devices that access information are essential for managing such information efficiently. Flash memory, with its advantages of low power consumption, high-speed operation, being readable/writable, non-volatile, and requiring no mechanical operations, has been widely applied to personal computers and electronic apparatus. Operations of data writing, reading, and erasing can be performed repeatedly on a non-volatile memory device and the data stored therein will not be lost even when a power supply is turned off.
Flash memory includes a plurality of flash cells, wherein each flash cell includes a MOS (Metal-Oxide-Semiconductor) transistor. Each MOS transistor includes a stacked gate structure having a floating gate and a control gate sequentially stacked on a semiconductor substrate. The floating gate and the control gate are isolated by an insulating layer, and the floating gate and the semiconductor substrate are isolated by a tunneling oxide (this is known as a stacked gate flash memory). A source region and a drain region are disposed in the semiconductor substrate at two sides of the stacked gate structure. In order to be erasable, each flash cell further includes an erase gate disposed beside the floating gate. For minimizing the size of the flash cell, the erase gate is usually disposed on the source region. An inter poly oxide is formed between the erase gate and the source region and between the erase gate and the floating gate to not only isolate the erase gate from the source region but also isolate the erase gate and the floating gate. Since that, the thickness of the inter poly oxide between the erase gate and the floating gate and the thickness of the inter poly oxide between the erase gate and the source region are the same. However, there is a tradeoff in the design of the thickness of the inter poly oxide in the conventional flash cell structure. That is, the erase operation of the flash cell structure is easily failed when the thickness of the inter poly oxide between erase gate and the floating gate is too thick, and the breakdown of the inter poly oxide between the erase gate and the source region is easily generated when the thickness of the inter poly oxide between the erase gate and the source region is too thin. Accordingly, to design a new flash cell structure to overcome this issue is an objective in this field.